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XC95144XL High Performance CPLD
Preliminary Product Specification
November 13, 1998 (Version 1.2)
Features
* * * * 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins) Optimized for high-performance 3.3 V systems - Low power operation - 5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V signals - 3.3 V or 2.5 V output capability - Advanced 0.35 micron feature size CMOS FastFLASHTM technology Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT IITM switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with 3 global and one productterm clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000 V Pin-compatible with 5 V-core XC95144 device in the 100-pin TQFP package
Power Estimation
Power dissipation in CPLDs can very substantially depending on the system frequency, design application, and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
*
Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in graphical form.
*
200
nce rma erfo hP Hig 104 MHz
178 MHz
Typical ICC (mA)
* * * *
150
100
Low P ow
er
50
*
Description
The XC95144XL is a 3.3 V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview.
0
50
150 100 Clock Frequency (MHz)
200
X5898C
Figure 1: Typical Icc vs. Frequency for XC95144XL
November 13, 1998 (Version 1.2)
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XC95144XL High Performance CPLD
3 JTAG Port 1
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 4
54 18
Function Block 3 Macrocells 1 to 18
54 18
Function Block 4 Macrocells 1 to 18
54 18
Function Block 8 Macrocells 1 to 18
X5922B
Figure 2: XC95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
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November 13, 1998 (Version 1.2)
Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature Value -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 -65 to +150 +260 +150 Units V V V
oC o o
C C
Note 1: Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to +7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol VCCINT VCCIO VIL VIH VO Parameter Supply voltage for internal logic Commercial TA = 0oC to 70oC and input buffers Industrial TA = -40oC to +85oC Supply voltage for output drivers for 3.3 V operation Supply voltage for output drivers for 2.5 V operation Low-level input voltage High-level input voltage Output voltage Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.80 5.5 VCCIO Units V V V V V V V
Quality and Reliability Characteristics
Symbol tDR NPE VESD Parameter Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Min 20 10,000 2,000 Max Units Years Cycles Volts
DC Characteristics Over Recommended Operating Conditions
Symbol VOH VOL IIL IIH CIN ICC Parameter Output high voltage for 3.3 V outputs Output high voltage for 2.5 V outputs Output low voltage for 3.3 V outputs Output low voltage for 2.5 V outputs Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA IOH = -500 A IOL = 8.0 mA IOL = 500 A VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 90% VCCIO Max Units V V V V A A pF ma
0.4 0.4 10.0 10.0 10.0 45
November 13, 1998 (Version 1.2)
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XC95144XL High Performance CPLD
AC Characteristics
Symbol tPD tSU tH tCO fSYSTEM tPSU tPH tPCO tOE tOD tPOE tPOD tAO tPAO tWLH tPLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) XC95144XL-5 Max1 Min1 5.0 3.7 0.0 3.5 178.6 1.7 2.0 5.5 4.0 4.0 7.0 7.0 10.0 10.5 2.8 5.0 Advance XC95144XL-7 XC95144XL-10 Min Max Min Max 7.5 10.0 4.8 6.5 0.0 0.0 4.5 5.8 125.0 100.0 1.6 2.1 3.2 4.4 7.7 10.2 5.0 7.0 5.0 7.0 9.5 11.0 9.5 11.0 12.0 14.5 12.6 15.3 4.0 4.5 6.5 7.0 Preliminary Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns
Note 1:Please contact Xilinx for up-to-date information on advance specifications.
VTEST R1 Device Output R2 CL
Output Type
VCCIO 3.3 V 2.5 V
VTEST 3.3 V 2.5 V
R1 320 250
R2 360 660
CL 35 pF 35 pF
X5906A
Figure 3: AC Load Circuit
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November 13, 1998 (Version 1.2)
Internal Timing Parameters
Symbol Parameter XC95144XL-5 Max1 Min1 1.5 1.1 2.0 4.0 2.0 0.0 1.6 1.0 5.5 0.5 2.3 1.4 2.3 1.4 0.4 6.0 5.0 1.0 5.0 1.9 7.5 1.4 6.4 3.5 0.8 4.0 Preliminary 2.6 2.2 2.6 2.2 0.5 6.4 10.0 1.8 7.3 4.2 1.0 4.5 XC95144XL-7 Min Max 2.3 1.5 3.1 5.0 2.5 0.0 2.4 1.4 7.2 1.3 3.0 3.5 3.0 3.5 1.0 7.0 XC95144XL-10 Min Max 3.5 1.8 4.5 7.0 3.0 0.0 2.7 1.8 7.5 1.7 Units
Buffer Delays Input buffer delay tIN GCK buffer delay tGCK GSR buffer delay tGSR GTS buffer delay tGTS Output buffer delay tOUT Output buffer enable/disable delay tEN Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial Delays Combinatorial logic propagation delay tPDI Register setup time tSUI Register hold time tHI tECSU Register clock enable setup time tECHO Register clock enable hold time Register clock to output valid time tCOI Register async. S/R to output delay tAOI Register async. S/R recover before clock tRAI tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays FastCONNECT IITM feedback delay tF Time Adders Incremental product term allocator delay tPTA tSLEW Slew-rate limited delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.7 3.0 Advance Note 1: Please contact Xilinx for up-to-date information on advance specifications.
November 13, 1998 (Version 1.2)
5
XC95144XL High Performance CPLD
XC95144XL I/O Pins
BScan Function Macrocell TQ100 TQ144 CS144 Order Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 11 12 - 13 14 15 16 - 17 18 - 19 20 - 22 - - 99 - - 1 2 - 3 4 - 6 7 - 8 9 - 10 - 23 16 17 25 19 20 21 22 31 24 26 27 28 35 30 - 142 143 4 2 3 5 6 7 9 10 12 11 13 14 15 - H3 F1 G2 J1 G3 G4 H1 H2 K3 H4 J2 J3 J4 M1 K2 C3 A2 C1 B1 C2 D4 D3 D2 E4 E3 E1 E2 F4 F3 F2 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 [1] [1] [1] [1] [1] [1] Notes BScan Function Macrocell TQ100 TQ144 CS144 Order Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 23 - - 24 25 - 27 28 - 29 30 - 32 33 - 34 - - 87 - - 89 90 - 91 92 - 93 94 - 95 96 - 97 39 32 41 44 33 34 46 38 40 48 43 45 49 50 51 - 118 126 133 128 129 130 131 135 132 134 137 136 138 139 140 M3 L1 K4 N4 L2 L3 L5 N2 N3 N5 M4 K5 K6 L6 M6 C9 A7 A5 D7 A6 B6 C6 C5 D6 B5 A4 D5 B4 C4 A3 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 [1] [1] Notes
Note 1: Global control pin.
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November 13, 1998 (Version 1.2)
XC95144XL (Continued)
BScan Function Macrocell TQ100 TQ144 CS144 Order Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 35 - - 36 37 - 39 40 - 41 42 - 43 46 - 49 - - 74 - - 76 77 - 78 79 - 80 81 - 82 85 - 86 - 52 59 53 54 66 56 57 68 58 60 70 61 64 69 - - 106 111 110 112 113 116 115 119 120 121 124 117 125 - N6 L8 M7 N7 M10 K7 N8 N11 M8 K8 L11 N9 K9 M11 C11 B11 A12 A11 D10 A10 B10 B9 A9 D8 A8 D9 B7 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Notes BScan Function Macrocell TQ100 TQ144 CS144 Order Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 50 - - 52 53 - 54 55 - 56 58 - 59 60 - 61 - - 63 - - 64 65 - 66 67 - 68 70 - 71 72 - 73 - - 71 75 74 76 77 78 80 79 82 85 81 86 87 83 88 - - 91 95 97 92 93 94 96 101 98 100 103 102 104 107 105 - N12 L12 M13 L13 K10 K11 K13 K12 J11 H10 J10 H11 H12 J12 H13 G11 F11 E13 G10 F13 F12 F10 D13 E12 E10 D11 D12 C13 B13 C12 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 Notes
November 13, 1998 (Version 1.2)
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XC95144XL High Performance CPLD
XC95144XL Global, JTAG and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 3.3 V VCCIO 2.5 V/3.3 V GND No Connects TQ100 TQ144 CS144 22 30 K2 23 32 L1 27 38 N2 3 5 D4 4 6 D3 1 2 B1 2 3 C2 99 143 A2 48 67 L10 45 63 L9 83 122 C8 47 65 N10 5, 57, 98 8, 42, 84, 141 B3, D1, J13, L4 26, 38, 51, 88 1, 37, 55, 73, 109, 127 A1, A13, C7, L7, N1, N13 21, 31, 44, 62, 69, 75, 84, 18, 29, 36, 47, 62, 72, 89, B2, B8, B12, C10, E11, 100 90, 99, 108, 114, 123, 144 G1, G12, G13, K1, M2, M5, M9, M12 - -
Ordering Information
Example:
Device Type
XC95144XL -7 TQ 100 C
Temperature Range Number of Pins
Speed Grade
Package Type
Speed Options -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay -5 5 ns pin-to-pin delay
Packaging Options TQ100 100-Pin Thin Quad Flat Pack (TQFP) TQ144 144-Pin Thin Quad Flat Pack (TQFP) CS144 144-Pin Chip Scale Package (CSP) Temperature Options C= Commercial TA = 0oC to +70oC I = Industrial TA = -40oC to +85oC
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November 13, 1998 (Version 1.2)
Component Availability
Pins Type Code XC95144XL -10 -7 -5 100 Plastic TQFP TQ100 C, I C (C) 144 Plastic TQFP TQ144 C, I C (C) 144 Chip Scale Package CSP CS144 (C) -
C = Commercial (TA = 0oC to +70oC) I = Industrial (TA = -40oC to +85oC) ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date availability information.
Revision History
Date 10/30/98 11/13/98 Revision Minor corrections in CS144 pinout table. V1.2 Minor correction in CS144 pinout table.
November 13, 1998 (Version 1.2)
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